Various embodiments of the present invention relate to data processing, and more specifically, to a method and apparatus for allocating computing elements in a data receiving link.
With the development of wireless communication technology, considerable progress has been achieved in both hardware and software in a communication system. As a result, a wireless communication network can provide increasingly high transmission bandwidths, and transmission delays in the wireless communication network are reduced greatly. Technological advances bring about many conveniences to massive users and can support various applications in a mobile terminal. With respect to a mobile terminal, as its data processing capacity grows stronger, requirements on real time transmission of data by various application programs installed on the mobile terminal also tend to get higher. In the meanwhile, the number of mobile terminal users increases constantly. Therefore, high requirements are imposed on the data processing capacity of a wireless network.
A device (e.g. a receiver, etc.) in an existing wireless communication network is usually implemented based on a dedicated hardware device, which may include, for example, a dedicated chip, an adaptor, an accelerator, etc; moreover, it is possible to involve a dedicated digital signal processing (DSP) circuit and/or a field programmable gate array (FPGA), etc. Although the receiver may further include software processing modules, since these software processing modules are developed based on dedicated hardware devices, they cannot use a parallel data processing algorithm supported by a general-purpose processor.
It should be understood that with the increase of a general-purpose computer hardware processing capacity, techniques such as a multi-core processor and a computer cluster provide strong physical support for parallel data processing, and the parallel data processing capacity based on general-purpose processors has been improved by a large margin. Regarding the wireless communication field, although dedicated hardware architectures in communication devices have made huge contribution to the data processing capacity improvement, they restrict to some extent the application of general-purpose parallel data processing algorithms. In view of the status quo and development trend, it becomes a brand-new research area as to how to introduce into wireless communication devices a general-purpose data processor and further a general-purpose parallel data processing algorithm. At this point, how to schedule these computing elements and further enhance the data processing efficiency becomes a focus of attention.